1. Field of the Invention
The present invention relates to a method of forming a capacitor and a contact plug, and more particularly, to a method of forming a capacitor and a contact plug at the same step.
2. Description of the Prior Art
A typical dynamic random access memory (DRAM) cell comprises a metal-oxide-semiconductor field effect transistor (FET) and a capacitor formed on a silicon semiconductor substrate, which makes the source of the FET electrically connect the charge-storage electrode plate of the capacitor. A DRAM is completed by gathering a plurality of the memory cells to form a memory cell array and is operated in accordance with peripheral circuits such as sensitive amplifiers.
By request of increasing the integration of DRAM in recent years, the area of the memory cell is reduced and thereby the size of the FET and capacitor should be lessened. In order to keep the capacitance appropriate in the narrow memory cell, it merely can develop the capacitor upwardly and which causes an upward movement of a metallic-conducting layer that simultaneously connects the upper electrode plate and a source/drain region of the peripheral circuits. Since this design would not lengthen the distance between the upper electrode plate and the metallic-conducting layer, it will not increase the difficulty in an etching process for forming a contact plug that provides the connection between the upper electrode plate and the metallic-conducting layer. However, this design would greatly lengthen the distance between the source/drain region of the peripheral circuits and the metallic-conducting layer, thereby another contact plug with greater aspect ratio formed by complicated process with two masks is needed for connecting the source/drain region and the metallic-conducting layer.
Please refer to FIG. 1A to FIG. 1G, FIG. 1A to FIG. 1G are schematic cross-sectional diagrams of forming a crown-shaped capacitor and a contact plug according to the prior art. As shown in FIG. 1A, a thermal oxidation process, such as local oxidation (LOCOS), is firstly performed on a p-type silicon substrate 100 to form a field-insulating layer (not shown) for isolating an active area. The active region comprises a memory cell area 102 and a peripheral circuit area 104. Next, conventional semiconductor processes, such as deposition, photolithography and ion-implantation, are performed on the active region in sequence to form a transistor (not shown), a bit line 112, a first contact plug 115, and a first insulating layer 120. The transistor has a gate and a diffusion region. The gate comprises a doped polysilicon layer and a silicide layer. The diffusion region comprises a first source/drain region 110 in the memory cell area 102, and a second source/drain region 111 in the peripheral circuit area 104. The bit line 112 formed of tungsten is connected with other memory cell. The first contact plug 115 is connected with the second source/drain region 111. Then, a second contact plug 118 formed of doped polysilicon is fabricated in the memory cell area 102 for connecting the first source/drain region 110. Then, a second insulating layer 122 formed of BPSG is deposited to cover the first insulating layer 120 and followed by a planarization process. Next, in a photolithography process, a photo resist layer (not shown) is coated and patterned on the second insulating layer 120, and then an etching process is performed to form a first opening 150 that passes through the second insulating layer 122 till exposing the top surface of the second contact plug 118. The photoresist layer is then removed.
As shown in FIG. 1B, a first conducting layer 142 is deposited on the second insulating layer 122 and the sidewall and bottom of the first opening 150 to connect the second contact plug 118. The first conducting layer 142 formed of tungsten.
As shown in FIG. 1C, another photoresist layer (not shown) is coated on the first conducting layer 142 and filling the first opening 150, and then a chemical mechanical polishing (CMP) method is used to remove the photoresist layer and the first conducting layer 142 positioned on the second insulating layer 122 except the portion those positioned in the first opening 150. Next, the photoresist layer remaining in the first opening 150 is removed and the first conducting layer 142' remaining in the first opening 150 is kept.
As shown in FIG. 1D, the second insulating layer 122 is patterned by a photolithography process and then partial of the second insulating layer 122 positioned on the first insulating layer 120 in the memory cell area 102 is etched away to expose the remaining first conducting layer 142'. The part 142' serves as a bottom electrode plate 170 of the crown-shaped capacitor.
As shown in FIG. 1E, a dielectric layer 175 is deposited on the surface of the bottom electrode plate 170, the second insulating layer 122 and the first insulating layer 120. Next, a second conducting layer 180 is deposited on the dielectric layer 175 to form an upper electrode plate 180 of the crown-shaped capacitor. This completed the crown-shaped capacitor in the memory cell area 102. Then, the dielectric layer 175 and the second conducting layer 180 positioned in the peripheral circuit area 104 is patterned and etched away.
As shown in FIG. 1F, a third insulating layer 124 formed of BPSG is deposited to cover the second insulating layer and the upper electrode plate 180, and then a planarization process is performed. Next, the third insulating layer 124 is patterned and etched to form a first contact window 152 passing through the third insulating layer 124 till exposing the upper electrode plate 180.
As shown in FIG. 1G, a photolithography is performed to pattern a second contact window 154 that passes through the third insulating layer 124, the second insulating layer 122 and partial of the first insulating layer 120 till exposing the top surface of first contact plug 115. However, at this step of forming the second contact window 154 having a great depth, it is difficult to control an etching stop and thus causes an incomplete etching. This will result in defects and a short circuit. A shielding layer 160 is deposited afterward by a physical vapor deposition (PVD) method to cover the surface of the third insulating layer 124, the first contact window 152 and the second contact window 154. Finally, a third conducting layer 144 is deposited on the shielding layer 160 by the PVD method to fill the first contact window 152 and the second contact window 154. The third conducting layer 144 in the first contact window 152 is used as a contact plug 184 for connecting the third conducting layer 144 and the upper electrode plate 180. The third conducting layer 144 in the second contact window 154 is used as a contact plug 185 for connecting the third conducting layer 144 and the second source/drain region 111.
From the above-mentioned process, some shortcomings are found as described hereinafter. First, two masks operated in accordance with two etching steps are needed after completing the capacitor in the memory cell area 102. One mask is used to form the first contact window 152 for connecting the third conducting layer 144 and the upper electrode plate 180. Since the upper electrode plate 180 is close to the third conducting layer 144, this etching step is easily controlled. The other mask is used to form the second contact window 154 for connecting the third conducting layer 144 and the first contact plug 115 in the peripheral circuit area 104. Since a request of reducing the volume of the DRAM cell is demanded, the capacitor is developed upward to match each reduced element. Nevertheless, this increases the distance between the third conducting layer 144 and the source/drain region 111, and thereby the second contact window 154 with high aspect ratio is designed. Since the etching stop is hard to be controlled, it is very difficult in forming the deep and narrow contact window by only one etching step. Also, the incomplete etching is often found to cause a short circuit and thus will deprive the expected functions of the semiconductor device.
Second, the designed distance between the third conducting layer 144 and the source/drain region 111 is long, it is not easy to uniformly deposited the shielding layer 160 on the sidewall and bottom of the second contact window 154 by the PVD method. The uneven shielding layer 160 will make the contact plug 185 bring about spiking, electro-migration and short circuit. Also, it is hard to completely fill the second contact window 154 with the contact plug 185 by the PVD method, which will lead to a broken circuit between the third conducting layer 144 and the source/drain region 111 in the peripheral circuit area 104.
The above-described defects occur in the prior process are the most part of resulting in losing the expected function and decreasing the yield of the semiconductor product.